6.1. Processor CDP1802

6.1. Processor CDP1802
	Kapitola 6. COSMAC (RCA CDP1800 family)

Propis procesoru CDP1802

Vlastnosti

Čas vykonání instrukce Instruction Time 3.2µs
Provozní teploty od -40oC do +85oC
123 instrukcí, shora kompatibilní s CDP1802
BCD aritmetika
IDLE mód s nízkým příkonem
Vývodově kompatibilní s CDP1802 vyjma vývodu 16
Schopnost přímo adresovat 64KiB paměti
64B paměti na čipu ^[1]
šestnáct šestnáctibitových registrů
Na čipu integrovaný oscilátor. Krystalový, nebo RC.
8-mi bitový čítač/časovač

Tabulka 6.1. CDP1802 Opcodes řazeno podle operačních kódů

CODE	MNEMO	Instrukce	Cycle	Popis
`00`	`IDL`	Idle	2	Wait for DMA or interrupt; M[R₀)→BUS
`0N`	`LDN`	Load via N	2	M(R_N)→D; For N not 0
`1N`	`INC`	Increment Reg. N	2	R_N+1→R_N
`2N`	`DEC`	Decrement Reg. N	2	R_N-1→R_N
`30`	`BR`	Short Branch	2	M[R_P]→R_P.0
`31`	`BQ`	Short Branch if Q=1	2	If Q=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`32`	`BZ`	Short Branch if D=0	2	If D=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`33`	`BDF`	Short Branch if DF=1	2	If D=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`33`	`BGE`	Short Branch if Equal or Greater	2	If D=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`33`	`BPZ`	Short Branch if Pos. or Zero	2	If D=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`34`	`B1`	Short Branch if EF1=1	2	If EF1=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`35`	`B2`	Short Branch if EF2=1	2	If EF2=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`36`	`B3`	Short Branch if EF3=1	2	If EF3=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`37`	`B4`	Short Branch if EF4=1	2	If EF4=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`38`	`NBR`	No Short Branch (See SKP)	2	R_P+1→R_P
`38`	`SKP`	Short Skip (See NBR)	2	R_P+1→R_P
`39`	`BNQ`	Short Branch if Q=0	2	If Q=1 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3A`	`BNZ`	Short Branch if D not 0	2	If D not 0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3B`	`BM`	Short Branch if Minus	2	If D=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3B`	`BNF`	Short Branch if DF=0	2	If D=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3B`	`BPL`	Short Branch if Less	2	If D=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3C`	`BN1`	Short Branch if EF1=0	2	If EF1=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3D`	`BN2`	Short Branch if EF2=0	2	If EF2=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3E`	`BN3`	Short Branch if EF3=0	2	If EF3=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`3F`	`BN4`	Short Branch if EF4=0	2	If EF4=0 Then M[R_P]→R_P.0 Else R_P+1→R_P
`4N`	`LDA`	Load Advance	2	M(R_N)→D; R_N+1→R_N
`5N`	`STR`	Store via N	2	D→M(R_N)
`60`	`IRX`	Increment Reg. X	2	R_X+1→R_X
`61`	`OUT 1`	Output 1	2	M[R_X]→BUS; R_X+1→R_X; N Lines=1
`62`	`OUT 2`	Output 2	2	M[R_X]→BUS; R_X+1→R_X; N Lines=2
`63`	`OUT 3`	Output 3	2	M[R_X]→BUS; R_X+1→R_X; N Lines=3
`64`	`OUT 4`	Output 4	2	M[R_X]→BUS; R_X+1→R_X; N Lines=4
`65`	`OUT 5`	Output 5	2	M[R_X]→BUS; R_X+1→R_X; N Lines=5
`66`	`OUT 6`	Output 6	2	M[R_X]→BUS; R_X+1→R_X; N Lines=6
`67`	`OUT 7`	Output 7	2	M[R_X]→BUS; R_X+1→R_X; N Lines=7
`69`	`INP 1`	Input 1	2	BUS→M[R_X]; BUS→D; N Lines=1
`6A`	`INP 2`	Input 2	2	BUS→M[R_X]; BUS→D; N Lines=2
`6B`	`INP 3`	Input 3	2	BUS→M[R_X]; BUS→D; N Lines=3
`6C`	`INP 4`	Input 4	2	BUS→M[R_X]; BUS→D; N Lines=4
`6D`	`INP 5`	Input 5	2	BUS→M[R_X]; BUS→D; N Lines=5
`6E`	`INP 6`	Input 6	2	BUS→M[R_X]; BUS→D; N Lines=6
`6F`	`INP 7`	Input 7	2	BUS→M[R_X]; BUS→D; N Lines=7
`70`	`RET`	Return	2	M[R_X]→(X,P); R_X+1→R_X, 1→IE
`71`	`DIS`	Disable	2	M[R_X]→(X,P); R_X+1→R_X, 0→IE
`72`	`LDXA`	Load via X and Advance	2	M(R_X)→D; R_X+1→R_X
`73`	`STXD`	Store via X and Decrement	2	D→M(R_X); R_X-1→R_X
`74`	`ADC`	Add with Carry	2	M[R_X]+D+DF→(DF,D)
`75`	`SDB`	Subtract D with Borrow	2	M[R_X]-D-(not DF)→(DF,D)
`76`	`RSHR`	Ring Shift Right	2	shift D right, LSB(D)→DF, DF→MSB(D)
`76`	`SHRC`	Shift Right with Carry	2	shift D right, LSB(D)→DF, DF→MSB(D)
`77`	`SMB`	Subtract Memory with Borrow	2	D-M[R_X]-(not DF)→(DF,D)
`78`	`SAV`	Save	2	T→M[R_X]
`79`	`MARK`	Push X,P to Stack	2	(X,P)→T;(X,P)→M[R₂]; P→X; R₂-1→R₂
`7A`	`REQ`	Reset Q	2	0→Q
`7B`	`SEQ`	Set Q	2	1→Q
`7C`	`ADCI`	Add with Carry, Immediate	2	M[R_P]+D+DF→(DF,D); R_P+1→R_P
`7D`	`SDBI`	Subtract D with Borrow, Immediate	2	M[R_P]-D-(not DF)→(DF,D); R_P+1→R_P
`7E`	`RSHL`	Ring Shift Left	2	shift D left, MSB(D)→DF, DF→LSB(D)
`7E`	`SHLC`	Shift Left with Carry	2	shift D left, MSB(D)→DF, DF→LSB(D)
`7F`	`SMBI`	Subtract Memory with Borrow, Immediate	2	D-M[R_P]-(not DF)→(DF,D); R_P+1→R_P
`8N`	`GLO`	Get low Reg. N	2	R_N.0→D
`9N`	`GHI`	Get low Reg. N	2	R_N.1→D
`AN`	`PLO`	Put low Reg. N	2	D→R_N.0
`BN`	`PHI`	Put low Reg. N	2	D→R_N.1
`C0`	`LBR`	Long Branch	3	M[R_P]→R_P.1; M[R_P+1]→R_P.0
`C1`	`LBQ`	Long Branch if Q=1	3	If Q=1 Then M[R_P]→R_P.1; M[R_P+1]→R_P.0 Else R_P+2→R_P
`C2`	`LBZ`	Long Branch if D=0	3	If D=0 Then M[R_P]→R_P.1; M[R_P+1]→R_P.0 Else R_P+2→R_P
`C3`	`LBDF`	Long Branch if DF=1	3	If DF=1 Then M[R_P]→R_P.1; M[R_P+1]→R_P.0 Else R_P+2→R_P
`C4`	`NOP`	No Operation	3	Continue
`C5`	`LSNQ`	Long Skip if Q=0	3	If Q=0 Then R_P+2→R_P Else Continue
`C6`	`LSNZ`	Long Skip if D not 0	3	If D not 0 Then R_P+2→R_P Else Continue
`C7`	`LSNF`	Long Skip if DF=0	3	If DF=0 Then R_P+2→R_P Else Continue
`C8`	`LSKP`	Long Skip (See NLBR)	3	R_P+2→R_P
`C8`	`NLBR`	No Long (See LSKP)	3	R_P+2→R_P
`C9`	`LBNQ`	Long Branch if Q=0	3	If Q=0 Then M[R_P]→R_P.1; M[R_P+1]→R_P.0 Else R_P+2→R_P
`CA`	`LBNZ`	Long Branch if D not 0	3	If D not 0 Then M[R_P]→R_P.1; M[R_P+1]→R_P.0 Else R_P+2→R_P
`CB`	`LBNF`	Long Branch if DF=0	3	If DF=0 Then M[R_P]→R_P.1; M[R_P+1]→R_P.0 Else R_P+2→R_P
`CC`	`LSIE`	Long Skip if IE=1	3	If IE=1 Then R_P+2→R_P Else Continue
`CD`	`LSQ`	Long Skip if Q=1	3	If Q=1 Then R_P+2→R_P Else Continue
`CE`	`LSZ`	Long Skip if D=0	3	If D=0 Then R_P+2→R_P Else Continue
`CF`	`LSDF`	Long Skip if DF=1	3	If DF=1 Then R_P+2→R_P Else Continue
`DN`	`SEP`	Set P	2	N→P
`EN`	`SEX`	Set X	2	N→X
`F0`	`LDX`	Load via X	2	M(R_X)→D
`F1`	`OR`	Or	2	M[R_X] OR D →D
`F2`	`AND`	And	2	M[R_X] and D →D
`F3`	`XOR`	Exclusive Or	2	M[R_X] xor D →D
`F4`	`ADD`	Add	2	M[R_X]+D→(DF,D)
`F5`	`SD`	Subtract D	2	M[R_X]-D→(DF,D)
`F6`	`SHR`	Shift Right	2	shift D right, LSB(D)→DF, 0→MSB(D)
`F7`	`SM`	Subtract Memory	2	D-M[R_X]→(DF,D)
`F8`	`LDI`	Load Immediate	2	M(R_P)→D; R_P+1→R_P
`F9`	`ORI`	Or Immediate	2	M[R_P] OR D →D; R_P+1→R_P
`FA`	`ANI`	And Immediate	2	M[R_P] and D →D; R_P+1→R_P
`FB`	`XRI`	Exclusive Or Immediate	2	M[R_P] xor D →D; R_P+1→R_P
`FC`	`ADI`	Add Immediate	2	M[R_P]+D→(DF,D); R_P+1→R_P
`FD`	`SDI`	Subtract D Immediate	2	M[R_P]-D→(DF,D); R_P+1→R_P
`FE`	`SHL`	Shift Left	2	shift D left, MSB(D)→DF, 0→LSB(D)
`FF`	`SMI`	Subtract Memory Immediate	2	D-M[R_P]→(DF,D); R_P+1→R_P

Tabulka 6.2. CDP1802 Opcodes řazeno podle operačních kódů

H\L	0	1	2	3
`0`	`IDL`	`LDN R1`	`LDN R2`	`LDN R3`	`LDN R4`	`LDN R5`	`LDN R6`	`LDN R7`	`LDN R8`	`LDN R9`	`LDN RA`	`LDN RB`	`LDN RC`	`LDN RD`	`LDN RE`	`LDN RF`
`1`	`INC R0`	`INC R1`	`INC R2`	`INC R3`	`INC R4`	`INC R5`	`INC R6`	`INC R7`	`INC R8`	`INC R9`	`INC RA`	`INC RB`	`INC RC`	`INC RD`	`INC RE`	`INC RF`
`2`	`DEC R0`	`DEC R1`	`DEC R2`	`DEC R3`	`DEC R4`	`DEC R5`	`DEC R6`	`DEC R7`	`DEC R8`	`DEC R9`	`DEC RA`	`DEC RB`	`DEC RC`	`DEC RD`	`DEC RE`	`DEC RF`
`3`	`BR`	`BQ`	`BZ`	`BDF`	`B1`	`B2`	`B3`	`B4`	`NBR`	`BNQ`	`BNZ`	`BM`	`BN1`	`BN2`	`BN3`	`BN4`
`4`	`LDA R0`	`LDA R1`	`LDA R2`	`LDA R3`	`LDA R4`	`LDA R5`	`LDA R6`	`LDA R7`	`LDA R8`	`LDA R9`	`LDA RA`	`LDA RB`	`LDA RC`	`LDA RD`	`LDA RE`	`LDA RF`
`5`	`STR R0`	`STR R1`	`STR R2`	`STR R3`	`STR R4`	`STR R5`	`STR R6`	`STR R7`	`STR R8`	`STR R9`	`STR RA`	`STR RB`	`STR RC`	`STR RD`	`STR RE`	`STR RF`
`6`	`IRX`	`OUT 1`	`OUT 2`	`OUT 3`	`OUT 4`	`OUT 5`	`OUT 6`	`OUT 7`		`INP 1`	`INP 2`	`INP 3`	`INP 4`	`INP 5`	`INP 6`	`INP 7`
`7`	`RET`	`DIS`	`LDXA`	`STXD`	`ADC`	`SDB`	`RSHR`	`SMB`	`SAV`	`MARK`	`REQ`	`SEQ`	`ADCI`	`SDBI`	`RSHL`	`SMBI`
`8`	`GLO R0`	`GLO R1`	`GLO R2`	`GLO R3`	`GLO R4`	`GLO R5`	`GLO R6`	`GLO R7`	`GLO R8`	`GLO R9`	`GLO RA`	`GLO RB`	`GLO RC`	`GLO RD`	`GLO RE`	`GLO RF`
`9`	`GHI R0`	`GHI R1`	`GHI R2`	`GHI R3`	`GHI R4`	`GHI R5`	`GHI R6`	`GHI R7`	`GHI R8`	`GHI R9`	`GHI RA`	`GHI RB`	`GHI RC`	`GHI RD`	`GHI RE`	`GHI RF`
`A`	`PLO R0`	`PLO R1`	`PLO R2`	`PLO R3`	`PLO R4`	`PLO R5`	`PLO R6`	`PLO R7`	`PLO R8`	`PLO R9`	`PLO RA`	`PLO RB`	`PLO RC`	`PLO RD`	`PLO RE`	`PLO RF`
`B`	`PHI R0`	`PHI R1`	`PHI R2`	`PHI R3`	`PHI R4`	`PHI R5`	`PHI R6`	`PHI R7`	`PHI R8`	`PHI R9`	`PHI RA`	`PHI RB`	`PHI RC`	`PHI RD`	`PHI RE`	`PHI RF`
`C`	`LBR`	`LBQ`	`LBZ`	`LBDF`	`NOP`	`LSNQ`	`LSNZ`	`LSNF`	`NLBR`	`LBNQ`	`LBNZ`	`LBNF`	`LSIE`	`LSQ`	`LSZ`	`LSDF`
`D`	`SEP R0`	`SEP R1`	`SEP R2`	`SEP R3`	`SEP R4`	`SEP R5`	`SEP R6`	`SEP R7`	`SEP R8`	`SEP R9`	`SEP RA`	`SEP RB`	`SEP RC`	`SEP RD`	`SEP RE`	`SEP RF`
`E`	`SEX R0`	`SEX R1`	`SEX R2`	`SEX R3`	`SEX R4`	`SEX R5`	`SEX R6`	`SEX R7`	`SEX R8`	`SEX R9`	`SEX RA`	`SEX RB`	`SEX RC`	`SEX RD`	`SEX RE`	`SEX RF`
`F`	`LDX`	`OR`	`AND`	`XOR`	`ADD`	`SD`	`SHR`	`SM`	`LDI`	`ORI`	`ANI`	`XRI`	`ADI`	`SDI`	`SHL`	`SMI`

^[1]jen procesor CDP1805


Kapitola 6. COSMAC (RCA CDP1800 family)		6.2. Processor CDP1805